1. Field of the Invention
The present invention generally relates to use of active power management of a memory subsystem. More particularly, the present invention relates to how memory devices distinguish between various power states and how these power states are utilized.
2. Discussion of the Related Art
As computer devices and systems continue to advance and become more complex, effective and efficient power and thermal management of computer devices and systems have become more and more critical in system design and implementation. Because computer devices and systems can only operate properly and safely within certain electrical power and temperature ranges, it is important to ensure that there is sufficient power supplied to operate various devices when needed. In addition, it is also important to ensure that thermal conditions do not exceed some threshold levels that are considered safe for the operations of these various devices. In general, computer devices, such as memory devices, are designed to have different operating modes or power states that correspond to different levels of performance and power consumption. The different operating modes or power states may include, for example, active mode, standby mode, nap mode, etc.
Generally, devices operate faster in active mode (or normal mode) than they do in the other modes. However, devices also consume more power and generate more heat in the active mode than they do in the other modes. Keeping all devices in the system in active mode reduces operational latency, and therefore improves overall system performance. But, keeping all devices in active mode consumes more power and generates more heat. In addition, even if the system power supply source is sufficient to power all devices in the system, some of these devices may be idle anyway, and therefore, it would be a waste of resources to keep them in active mode all the time. System performance requirements and system power usage requirements need to be balanced. To maintain a balance between system performance and system power usage and heat generation, it is necessary to keep some number of devices in an inactive mode to reduce power usage and heat. Depending on the applications and the operational environment, the number of devices to be kept in inactive mode may vary.
The system constraints and tradeoffs described above with respect to computer devices in general apply equally to memory devices in a memory system. In their active (i.e., normal) or most power-consuming mode, memory devices, such as Dynamic Random Access Memory (DRAM) devices, operate faster than they do when they are in inactive mode (e.g., standby, or nap mode). However, DRAM devices in active mode also consume far more power than when in inactive mode. As a result, to maintain a balance between performance and power consumption (and heat generation), some fixed number of DRAM devices may need to be kept in an inactive mode to conserve power and to reduce heat generation.
The use of multiple power states in memory devices, and in a DRAM device specifically, has been utilized. With multiple power states, varying levels of lower-than-active mode power consumption may be utilized by the memory device. Typically, a memory controller provides specific information as to what power state, including which level (if applicable) of the lower-than-active mode power state, the memory device should enter. However, having the memory controller provide specific information as to which lower-than-active mode (or lower-than-normal mode) power state the memory device should enter increases the complexity of memory controller.
Accordingly, there is a need for a memory system where multiple power states may be utilized while reducing the complexity of a memory controller.